? 2005 fairchild semiconductor corporation ds005105 www.fairchildsemi.com september 1983 revised january 2005 mm74hc14 hex inverting schmitt trigger mm74hc14 hex inverting schmitt trigger general description the mm74hc14 utilizes advanced silicon-gate cmos technology to achieve the low power dissipation and high noise immunity of standard cmos, as well as the capability to drive 10 ls-ttl loads. the 74hc logic family is functionally and pinout compatible with the standard 74ls logic family. all inputs are protected from damage due to static discharge by internal diode clamps to v cc and ground. features typical propagation delay: 13 ns wide power supply range: 2?6v low quiescent current: 20 a maximum (74hc series) low input current: 1 a maximum fanout of 10 ls-ttl loads typical hysteresis voltage: 0.9v at v cc = 4.5v ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. pb-free package per jedec j-std-020b. connection diagram pin assignments for dip, soic, sop and tssop top view logic diagram order number package package description number mm74hc14m m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow mm74hc14mx_nl m14a pb-free 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow mm74hc14sj m14d pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide mm74hc14mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide mm74hc14mtcx_nl mtc14 pb-free 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide mm74hc14n n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide mm74hc14n_nl n14a pb-free 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 mm74hc14 absolute maximum ratings (note 1) (note 2) recommended operating conditions note 1: absolute maximum ratings are those values beyond which dam- age to the device may occur. note 2: unless otherwise specified all voltages are referenced to ground. note 3: power dissipation temperature derating ? plastic ? n ? package: ? 12 mw/ c from 65 c to 85 c. dc electrical characteristics (note 4) note 4: for a power supply of 5v 10% the worst case output voltages (v oh , and v ol ) occur for hc at 4.5v. thus the 4.5v values should be used when designing with this supply. worst case v ih and v il occur at v cc = 5.5v and 4.5v respectively. (the v ih value at 5.5v is 3.85v.) the worst case leakage cur- rent (i in , i cc , and i oz ) occur for cmos at the higher voltage and so the 6.0v values should be used. supply voltage (v cc ) ? 0.5 to + 7.0v dc input voltage (v in ) ? 1.5 to v cc + 1.5v dc output voltage (v out ) ? 0.5 to v cc + 0.5v clamp diode current (i ik , i ok ) 20 ma dc output current, per pin (i out ) 25 ma dc v cc or gnd current, per pin (i cc ) 50 ma storage temperature range (t stg ) ? 65 c to + 150 c power dissipation (p d ) (note 3) 600 mw s.o. package only 500 mw lead temperature (t l ) (soldering 10 seconds) 260 c min max units supply voltage (v cc )26v dc input or output voltage 0 v cc v (v in , v out ) operating temperature range (t a ) ? 40 + 85 c symbol parameter conditions v cc t a = 25 ct a = ? 40 to 85 ct a = ? 55 to 125 c units typ guaranteed limits v t + positive going minimum 2.0v 1.2 1.0 1.0 1.0 v threshold voltage 4.5v 2.7 2.0 2.0 2.0 v 6.0v 3.2 3.0 3.0 3.0 v maximum 2.0v 1.2 1.5 1.5 1.5 v 4.5v 2.7 3.15 3.15 3.15 v 6.0v 3.2 4.2 4.2 4.2 v v t ? negative going minimum 2.0v 0.7 0.3 0.3 0.3 v threshold voltage 4.5v 1.8 0.9 0.9 0.9 v 6.0v 2.2 1.2 1.2 1.2 v maximum 2.0v 0.7 1.0 1.0 1.0 v 4.5v 1.8 2.2 2.2 2.2 v 6.0v 2.2 3.0 3.0 3.0 v v h hysteresis voltage minimum 2.0v 0.5 0.2 0.2 0.2 v 4.5v 0.9 0.4 0.4 0.4 v 6.0v 1.0 0.5 0.5 0.5 v maximum 2.0v 0.5 1.0 1.0 1.0 v 4.5v 0.9 1.4 1.4 1.4 v 6.0v 1.0 1.5 1.5 1.5 v v oh minimum high level v in = v il 2.0v 2.0 1.9 1.9 1.9 v output voltage |i out | = 20 a 4.5v 4.5 4.4 4.4 4.4 v 6.0v 6.0 5.9 5.9 5.9 v v in = v il |i out | = 4.0 ma 4.5v 4.2 3.98 3.84 3.7 v |i out | = 5.2 ma 6.0v 5.7 5.48 5.34 5.2 v v ol maximum low level v in = v ih 2.0v 0 0.1 0.1 0.1 v output voltage |i out | = 20 a 4.5v 0 0.1 0.1 0.1 v 6.0v 0 0.1 0.1 0.1 v v in = v ih |i out | = 4.0 ma 4.5v 0.2 0.26 0.33 0.4 v |i out | = 5.2 ma 6.0v 0.2 0.26 0.33 0.4 v i in maximum input current v in = v cc or gnd 6.0v 0.1 1.0 1.0 a i cc maximum quiescent v in = v cc or gnd 6.0v 2.0 20 40 a supply current i out = 0 a
3 www.fairchildsemi.com mm74hc14 ac electrical characteristics v cc = 5v, t a = 25 c, c l = 15 pf, t r = t f = 6 ns ac electrical characteristics v cc = 2.0v to 6.0v, c l = 50 pf, t r = t f = 6 ns (unless otherwise specified) note 5: c pd determines the no load dynamic power consumption, p d = c pd v cc 2 f + i cc v cc , and the no load dynamic current consumption, i s = c pd v cc f + i cc . typical performance characteristics input threshold, v t + , v t ? , vs power supply voltage propagation delay vs power supply symbol parameter conditions typ guaranteed limit units t phl , t plh maximum propagation delay 12 22 ns symbol parameter conditions v cc t a = 25 ct a = ? 40 to 85 ct a = ? 55 to 125 c units typ guaranteed limits t phl , t plh maximum propagation 2.0v 60 125 156 188 ns delay 4.5v 13 25 31 38 ns 6.0v 11 21 26 32 ns t tlh , t thl maximum output rise 2.0v 30 75 95 110 ns and fall time 4.5v 8 15 19 22 ns 6.0v 7 13 16 19 ns c pd power dissipation (per gate) 27 pf capacitance (note 5) c in maximum input capacitance 5 10 10 10 pf
www.fairchildsemi.com 4 mm74hc14 typical applications low power oscillator note: the equations assume t 1 + t 2 >> t pd0 + t pd1
5 www.fairchildsemi.com mm74hc14 physical dimensions inches (millimeters) unless otherwise noted 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m14a
www.fairchildsemi.com 6 mm74hc14 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m14d
7 www.fairchildsemi.com mm74hc14 physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc14
www.fairchildsemi.com 8 mm74hc14 hex inverting schmitt trigger physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n14a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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